Some applications of a buffer circuit involve receiving a differential input signal, conveying the signal and thereby generating a single-ended output signal, and driving the single-ended output signal to a low impedance load. Operation of the buffer circuit is to be highly linear. The buffer is to convey the signal confidently without contributing any significant distortion component over a wide input power range. Various different buffer circuits, and combinations of amplifier circuits, may be employed in an attempt to realize an overall buffer that has the desired characteristics and performance.
FIG. 1 (Prior Art) is a circuit diagram of one type of circuit that can be employed to realize the buffer. The circuit 1 is a common drain circuit 1 (also called a source follower). Circuit 1 is appropriate for driving a low impedance load because the circuit has a low output impedance, a high input impedance, and a large current gain. The output impedance is approximately equal to 1/gm, where gm is the transconductance of field effect transistor 2. The output voltage signal is developed across the current source 3 load. The circuit, however, only receives a single-ended signal. Accordingly, if this circuit is to be employed in an application as mentioned above where the input signal is a differential input signal, then another preceding stage is employed to receive the differential input signal, and to convert that differential signal into a single-ended signal VIN that can then be supplied onto the input lead 4 of the source follower circuit 1. The source follower circuit 1 in turn supplies a single-ended output signal VOUT via its output lead 5 to the low impedance load.
FIG. 2 (Prior Art) is a circuit diagram of a modified source follower circuit 6 that has even a lower output impedance. The circuit 6 of FIG. 2 is called a super source follower. As in the case of the source follower circuit 1 of FIG. 1, the first transistor 7 is in the common drain configuration. Capacitor 8 and resistor 9 are a biasing circuit. The AC component of the input signal VIN on input lead 10 is AC coupled by the capacitor 8 onto the gate of the first transistor 7. Resistor 9 allows the gate of the first transistor 7 to be DC biased to a first voltage VBIAS1. Transistor 11 functions as a current source in much the same way as current source 3 operates in the source follower circuit 1 of FIG. 1. The super source follower circuit of FIG. 2, as compared to the source follower circuit of FIG. 1, includes an additional P-channel field effect transistor 12, that acts as a current source, and an additional P-channel field effect transistor 13. These components reduce the output impedance of the overall circuit to approximately 1/(gm1*(1+gm2*ro12)), where gm1 is the transconductance of transistor 7, where gm2 is the transconductance of transistor 13, and where ro12 is the output impedance of transistor 12. As in the case of the conventional source follower circuit of FIG. 1, if the super source follower circuit 6 of FIG. 2 is used, then a preceding differential to single-ended (D2S) circuit may be employed to supply a single-ended signal onto the input lead 10 of the super source follower circuit 6. The super source follower circuit 6 supplies a single-ended output signal via its output lead 14 to the low impedance load.
FIG. 3 (Prior Art) is a diagram of another buffer circuit 15 that might be considered for use in receiving a differential input signal and outputting a single-ended signal to a low impedance load. Rather than receiving a differential input signal onto a first stage that outputs a single-ended signal so that a second stage source follower or super source follower can receive a single-ended input signal, the circuit 15 of FIG. 3 can receive the differential input signal directly onto input terminals 16 and 17. The circuit 15 of FIG. 3 outputs a differential output signal onto output terminals 18 and 19. The differential input signal is received by N-channel field effect transistors 20 and 21. N-channel field effect transistor 22 operates as a current source load for signal N-channel transistor 20. N-channel field effect transistor 23 operates as a current source load for signal N-channel transistor 21. The circuit 15 of FIG. 3, however, outputs a differential signal. If the circuit of FIG. 3 were to be used in the application mentioned above where a single-ended output signal is needed, then a second D2S stage may be employed to convert the differential output signal from the circuit 15 into the single-ended signal required to drive the low impedance load. This second stage, however, would consume additional power. Moreover, the second stage may not have an adequately low output impedance to drive the low impedance load with adequate linearity. Yet a third stage may therefore be required in order to drive the low impedance load without undue loss of buffer linearity. The circuit of FIG. 3 is therefore not really suitable for driving a single-ended signal onto a low impedance load, where the buffer is to be highly linear over a wide range of output power levels.
FIG. 4 (Prior Art) is a diagram of an improved version of the circuit of FIG. 3. The circuit 24 of FIG. 4 is referred to here as a differential hybrid voltage buffer or “DHVB”. A differential input signal is received onto input leads 25 and 26. The circuit generates a differential output signal that is output via output leads 27 and 28. The VIN+ component of the input signal is not just received onto the gate of N-channel signal transistor 29 as in the case of FIG. 3, but rather the VIN+ component is of appropriate phase that it can control the N-channel transistor 30 in a signal amplification function. Transistor 30 is therefore not just used as a current source load as in the circuit of FIG. 3, but rather transistor 30 is used for signal amplification. Likewise, the VIN− component of the input signal is not just received onto the N-channel signal transistor 31 as in the case of FIG. 3, but rather the VIN− component of the input signal is of appropriate phase that it is made to control the N-channel transistor 32. The N-channel transistor 32 does not just operate as current source load as in the case of FIG. 3, but rather in the case of FIG. 4 the N-channel transistor 32 operates as an amplifier and contributes to the output signal. The N-channel transistors 29 and 31 are in the common drain configuration. The N-channel transistors 30 and 32 are in the common source configuration. Because the buffer circuit of FIG. 4 is a mix of two circuit topologies, the circuit is called a differential “hybrid” voltage buffer circuit or “DHVB”. Due to all four transistors operating as amplifiers, the circuit of FIG. 4 for a given supply voltage and transistor size will generally output a higher output voltage swing as compared to the circuit of FIG. 3 if the two circuits are using the same supply voltage, and have the same transistor sizes, and are driving the same load. In addition, it is recognized that the signal in one leg of the circuit of FIG. 4 has two components. One component is due to the common source configuration transistor as driven by one part of the differential signal and the other component is due to the common drain configuration transistor as driven by the other part of the differential signal. Because the DHVB circuit combines the inverted signal of the common source stage from VIN+ and the noninverted signal of the source follower stage from VIN−, it can achieve higher gain and lower noise figure (NF) as compared to the circuit 15 of FIG. 3. In the DHVB circuit of FIG. 4, there is partial cancellation of the third derivative (gm″) of the output current due to the combining of the inverted signal of common source transistor with the noninverted signal of the source follower transistor. Because the linearity of the circuit is dominated by the gm″ nonlinearity, the DHVB circuit may exhibit a remarkable linearity improvement while simultaneously achieving low power consumption.
Unfortunately, as in the case of the differential signal output circuit 15 of FIG. 3, if the circuit 24 of FIG. 4 were to be used in the application mentioned above, then another one or more stages would typically be required in order to convert the differential output of the circuit 24 into the single-ended output signal need to drive the low impedance load. The DHVB circuit 24 of FIG. 4, which outputs a differential output signal, is therefore not generally suitable for use in an application where the circuit is to receive a differential input signal and is to drive a single-ended output signal to a low impedance load in such a way that the circuit is highly linear over a wide range of output powers.